IBM unveils record-breaking chip with 100 billion transistors in less than 1 nanometer footprint

IBM unveiled a 0.7 nm NanoStack chip carrying 100 billion transistors through an ambitious three-dimensional architecture ...
Interesting Engineering on MSN

New gallium nitride chip platform helps engineers get chip designs right the first time

Keysight Technologies and WIN Semiconductors have introduced a joint design workflow that aims to ...
Electronic Design

True-3D Chip-Layout Editor Facilitates Stacking Of Disparate Wafers

Say you wanted to create a chip in which a processor fabricated in 32-nm process rules would be combined with memory done on a 65-nm process and analog blocks fabricated at 180 nm. This leads you to ...
Digi Times

Designing AI chips with AI, AlphaChip plays chip layout game

Google's innovative approach of using artificial intelligence to design AI chips is revolutionizing the semiconductor industry. The key to their AlphaChip system lies in its reinforcement learning ...
Digi Times

Maxeda Technology: utilizing AI technology to optimize chip layout design, enhancing chip design efficiency and performance

With the rapid development of various digital innovations such as Generative AI, the demand for high-performance chips in the market has surged dramatically, leading to increased complexity in chip ...
EurekAlert!

Darwin3: a large-scale neuromorphic chip with a novel ISA and on-chip learning

The top left shows a photo of the system test board, with a red box indicating Darwin3. The top right displays the top-level view of the chip layout, while below are the layout details of the main ...